Analog front-end for the voltmeter (3/3)

In the last part for the analog front-end I tried to make all in one simulation for my first prototype:

The voltage offset of the LT1167 input op amp is automatically trimmed with 3 additional op amps. The first one is used for an input buffer, the second one subtract output voltage from the input one and the third one is used as buffer to the VRef pin of the LT1167 which requires low resistance. Simulation results shows that a small resistor (R6) must be put in serial to R5 in order to minimize the offset.

The next stage is the automatic voltage range. One SPDT relay can be used to switch between the middle point of the voltage divider (1:10 ratio, range from 1.25 to 12V) or directly from the LT1167 output (1:1 ratio, range from 0-1.25V). The window comparator for triggering the voltage range switch is realized with 2xLT1011 comparators and uses 2 voltage references : +/- 1.25V. In the simulation is not used hysteresis settings for the comparators, but special attention should be taken for accurate switching.

The last stage is the level shifting. The input signal is shifted by 0.625V, taken after the 1:2 divider from Vref source. The output of the stage have additional 1:2 voltage divider. 

All resistors will be from LT5400 quad matches series, which have matched long term drift of 2ppm. 

Here are examples for calculation of unknown input voltage when the output voltage is read out from the ADC using the simulation results:

Vin = (Vshift - Vout) * 2 when voltage range is 0-1.25V and input signal is positive:

Vout = 0.62499988 V 

Calculated Vin = 0.0000024V

Simulation Vin = 0V, error is 2.4 ppm

Vout = 0.12500075V

Calculated Vin = 0.9999985V

Simulation Vin = 1V, error is 1.5 ppm

Vin = (Vshift - Vout) * 10* 2 when voltage range is 1.25-12.0V and input signal is positive:

Vout = 0.024990104V

Calculated Vin = 12.00019792V

Simulation Vin = 12V, error is 16.49 ppm

Vin = -(Vout - Vshift) * 2 when voltage range is 0-1.25V and input signal is negative:

Vout = 1.124999 V 

Calculated Vin = -0.999998V

Simulation Vin = -1V, error is 2 ppm

Vin = -(Vout - Vshift) * 10 * 2 when voltage range is 1.25-12V and input signal is negative:

Vout = 1.2250097 V 

Calculated Vin = -12.000194V

Simulation Vin = -12V, error is 16.16 ppm

When the Vout is less then the Vshift, the input voltage is positive and when Vout is greater then Vshift, the input voltage is negative.

Analog front-end for the voltmeter (2/3)

Handling the negative voltage

If multi-slope integrated ADC or ADC with true differential input are used in a voltmeter, there is no need for a special handling of the negative voltage.
However most of the ADC on the market supports only positive voltage input and have uni-polar power supply. In this case the analog front end should convert the negative voltage input to positive or to limit it to the minimum allowed voltage (usually limited by ESD protection diodes in the ADC to several hundred mV below the ground).

I spent a lot of research time for this part of design and found the following approaches:

• Full- or half-wave rectification of the input bipolar signal.
• Switching between none inverting op amp when signal is positive and inverting op amp when signal is negative, using comparator and relays.
• Setting negative voltage on the ADC's ground pin and level shifting the digital output pins. This approach can be seen in the LTC2442 datasheet, page 27/28 and can be used also for LTC 2440 according LT tech support.
• Level shifting of the input signal.
• Bipolar single ended to differential conversion.

The half-wave rectification is based on the over voltage protection schematics and it is the most cost effective variant. LTSpice simulation can be found here.

The current limiting resistor should be selected in this way that voltage across the Schottky diode should not exceed maximum allowed input voltage for the ADC. In this example this is -0.3V. The drawback of this solution is that the voltmeter will detect the negative voltage, but will not able to measure it.

An example for the full-wave rectification can be found in the LT1001 datasheet, on bottom of the page 9, where schematics of "Precision Absolute Value Circuit" is shown. LTSpice simulation can be found here.

This schematics have the following drawbacks:
- Requires 5 matched resistors. This is costly and very hard to achieved.
- Requires 2 op amp in the signal path. This will increase the noise.
- In the mV range, distortion of the signal can be seen in the simulation:

The second option relies on swapping input signal between two op amps using relays. LTSpice simulation can be found here.

This schematics have the same output like the full-wave rectification, but required only 2 matched resistors (LT5400-1) and 2 SPDT relays. When the input voltage is below the ground, the comparator will close relays for inverting op amp and will open those for none inverting op amp.

The next approach is the level shifting of the input signal. LTSpice simulation can be found here.


This method shift the input voltage using half of the reference ADC voltage.
The schematics use one op amp for the shifting, one for Vref buffering and 2 quad LT5400 matched resistors.

The input signal is inverted by the first op amp and level shifted from the positive input from buffered ADC voltage divided by 2. The output voltage is additionally divided by 2: from 2.5V peak to peak to 1.25V peak to peak and the lowest voltage is 0V.

The last method is single to differential conversion. This can be done with specialized op amp with differential outputs or with discrete op-amps.

If the ADC have to be buffered, information can be found in the comprehensive application note named "Buffer Op Amp to ADC Circuit Collection" from the Texas Instruments company. Also good source of information can be found in the Analog Devices's "The Data Conversion Handbook", chapter 6, Interfacing to Data Converters.

Analog front-end for the voltmeter (1/3)

Analog front-end of the voltmeter should provide the following functionality and properties:

• Over-voltage protection.
• Voltage range selection (manual or automatic).
• Handling the negative voltage if the ADC analog inputs accept only positive voltage.
• High input resistance.
• Low thermal EMF connection to the test leads when low voltage levels are measured. 

All electronic components for the analog front end should be carefully selected to avoid performance degradation of the ADC parameters like the noise and non-linearity.

Over-voltage protection

I was able to find two ways for over-voltage protection design:

• Using Schottky diodes: When the input voltage (the green line in the simulation) is above the positive power supply voltage (V+), the Schottky diode connected to the V+ is opening and it's forward current (the red line in the simulation) is limited from the protection resistor. In result the output voltage (the blue line in the simulation) will be clamped to value equal to the power supply voltage minus the forward voltage of the Schottky diode. When the input voltage becomes negative, the Schottky diode connected to the negative power supply voltage (V-) will be opening and will limit the negative overvoltage. LTSpice simulation can be found here.

• Using PTC thermistor in series to input and Metal-Oxide-Varistor (MOV) in parallel to the input. The MOV resistance depends on input voltage: when the voltage is above the clamping value, the resistance going low which form a short circuit. The short produce heat in the PTC which increase it's resistance and this opens the circuit and protect the ADC input.

Unfortunately both methods have the following drawbacks when high accuracy voltmeter has to be built:

- Standard Schottky diodes have relative big reverse leakage current, which influence on the op amp voltage offset. The worst thing is that the leakage increases with temperature very quickly, thus output voltage will depends on temperature controlled voltage offset. There are silicon carbide Shottky diodes which resolve this kind of problem, but they are difficult to buy and the forward voltage is greater then the internal ESD diodes. The lowest leakage schottky diode which I found was PADx series from Vishay/Siliconix which are not produced anymore. They have between 1 and 100 pA maximum reverse leakage current. Few replacements exists from the following companies: InterFET (DPADx), Firechild Semiconductor (FJH1101), Central Semiconductor Corp. (BAV45).

- Using PTC and MOV decrease the overall input resistance, because the MOV is connected in parallel to the op amp input and it's resistance is a few MOhms. 

Nice video for general multi-meter protection made David Jones from EEVBlog. It include also current range protection as well.

Fortunately during selection of input op amp, I found LT1167 op amp which can handle up to 100V only with current limit resistor 5K in series to the input. This op amp has nice features: 200/1000 GOhms min/typ input resistance, sub-nA current bias, 1/6 ppm typ/max gain nonlinearity and output offset trimming possibility for calibration.

Automatic Voltage range selection

Most of the ADC have reference voltage below 5 V and a special circuit should be implemented to put the input voltage within the ADC range.
This feature can be easy implemented with a comparator, voltage divider and several relays after the input op amp:

In the shown above LTSpice simulation, the comparator LT1011 have Vref = 1.25V set to the positive input. When the input voltage (the green line in the simulation) reach the Vref, the output of the comparator (the blue line in the simulation) becomes in logical low level and the switches SW1 and SW3 are closing, SW2 is opening. The output voltage (the red line in the simulation) will be connected in the middle point of the voltage divider. In result the output voltage never goes above the Vref limit. The output from the comparator must be read out from the micro controler in order to multiply the measured voltage from the ADC with the voltage divider ratio.  

When input signal is bipolar, window comparator should be used as this is shown in the following simulation: