DMM mode selection: schematics and base breadboarding (Part 3)

In this part I will explain the DMM mode selection schematics and will implement the base logic in a breadboard.

The schematic is given below:

There are 4 push buttons for each mode, with debounce circuit connected to Shmitt inverters. Output of the inverters are connected to one of the input of the OR logic gate. The second input is connected to GPIO pins of the microcontroller. By this way the DMM modes can be controlled via push buttons or via remote interface like GPIO/RS232/USB etc. Additional logic gates can be put here to disable/enable manual switch or remote control.

Every output of the OR gates are connected to own D flip-flop and to 4-input OR gate. The output of the 4 input OR gates is connected to CLK pin of every D flip-flop.

When one of the push button is connected, the clock signal is generated from the 4 input OR gate output. This clock signal will force every D flip-flip to "remember" his input until the next clock edge. By this way every time when one push button is pressed, only one of the D flip-flops output becomes logical 1 and the rest are in logical 0 state. This is what we needed according to the switch table in the part 1 : every mode connect one switch, except for 2W/4W resistance where the voltmeter switch must be closed as well:

Measurement	SW VM	SW CM	SW 2W	SW FB2W	SW FB4W
Voltage	CLOSED	OPEN	OPEN	OPEN	OPEN
Current	OPEN	CLOSED	OPEN	OPEN	OPEN
Resistance 2W	CLOSED	OPEN	CLOSED	CLOSED	OPEN
Resistance 4W	CLOSED	OPEN	OPEN	OPEN	CLOSED

This additional requirement can be realized with additional 2-input OR gate connected to the output of the 2W/4W D flip-flops and the output connected to another 2-input OR gate connected to Voltmeter D flip-flip. By this way, every time when the 2W/4W resistance is selected, the VM switch will be closed as well.  

The prototype which I made, contain 3 push buttons and output of the every D flip-flop is connected to LED. There is one more LED for CLK signal and one more push button for reset the state of all D flip-flop to 0: 

In the bread board the following IC are used:
- 74174 : 4 D flip-flops.
- 7414 : 6 Inverters with Shmitt inputs.
- 744075 : 3 x 3 input OR logic gate

DMM mode selection: How to make SPDT JFET switch (Part 2)

Following the previous post, I made experiments with JFET switches in single-pole dual-throw configuration. This kind of switches are used in 3 places: switching between voltage and current meters, 2W/4W input of the ohm-meter feedback schematics and in the voltage reference selection switch.

The problem with SPDT configuration using the JFET transistors is the glitches when switching between the two voltage sources. The only instrument which can be used for resolving this issue is oscilloscope, which I did not have until recently. Last 6 months I looking for low cost oscilloscope and finally bought the new Siglent SDS1202X-E :

It is very compact, 2 channel, 200MHz/1GSps oscilloscope with RS232/I2C/SPI/LIN/CAN free decoding options.

The goal of this experiment is to create glitch free SPDT switch using 2 JFET transistor J109 from OnSemi which I had. The SPDT switch connects at one moment only one of it's dual input:

To make this possible, two JFET transistor should be connected together at the Source pin, their Drain pins will be connected to the input voltages. At one time only one of the transistor will be open and the another will be closed. This is realized with signals in opposite direction (logical 1 and 0) which feed the comparators connected to the JFET gates. The positive power supply of the comparators is +15V and the negative is -15V.

Lets start with the push button which will switch between two inputs. I'm using the classic debounce circuit with RC in front of inverting schmitt trigger:

The channel 1 of the scope is connected before the schmitt trigger and channel 2 is connected after it. The scope clear shows that rise time after the RC is around 37 ms, but the signal after the schmitt trigger decrease it to 1.2us.

Next step is to generate two opposite signals every time when the push button is pressed. I will use one more inverter to produce this opposite signal:

In the scope, the first channel shows the signal after the inverter and the second channel shows the signal before the inverter.

Now I have to connect the opposite signals to the input of comparators and to look what will be shown in the output. The used comparator is LM393P with 10K pull-up resistors. The minus input of the comparators are connected to resistor divider which provided 1.5V threshold voltage.

Full schematics
(see the update at the end of the post regarding the diodes)

The output from the connected JFET transistors is 5V when the button is not pressed and -5V when it is pressed:

 If we zoom in to see the transition period we can see the following picture:

When the input voltage is going from +5 to -5V, there are glitches around the -5V with 4V peak to peak value.

If the positive supply of the comparators is decreased to +5V instead using +15V, the transition is much better:

No more glitches and about 130 ns fall time from +5V to -5V.

But when I looked into the transition from -5V to +5V, there are a still lot of glitches:

After increasing the pull-up resistor with 5K, the transition is much better, but still there is small glitch:

And finally after adding small 20pF capacitor between the gate and the ground, the result is much better:

The transition time is increased about 3 times, but the transition glitch is gone.

So the learned lesson is that glitches depends on comparator's positive power supply voltage, pull-up resistors and compensated capacitor between the gate and the ground. Probably using different JFET transistors will change transition picture as well, so the only way is to use always a scope to check for glitches.

Update 2 May 2018: This post was mainly dedicated to removing glitches during switching, but I never check with high resolution DMM if the output voltage is the same as the input one. At the time of writing this post I had only my 3.5 digits KEW 1012 DMM and there was no differences between output and input voltage. However, recently I made the same schematics for my mutli-voltage reference calibration PCB and found that there are several hundreds micro-volts difference measuring with 6.5 digits DMM. After playing with the LTSpice, the problem was resolved with adding a diode between the comparator output and the JFET gate and confirmed with the real measurement. Note that the diode must have minimal reserve current leakage or it is better to use JFET with Igss in the pA range as diode (shorting the Drain and the Source as catode and the Gate as anode). 

DMM mode selection (Part 1)

One of the last things, which I have to find out, is the way of switching between different DMM's measurements : voltage, current and resistance.

In the handheld digital multi-meters, a mechanical rotary selector is used.

In the bench-top DMM, modes are switching electronically with push buttons or with remote interfaces like GPIB/RS-232/USB. This kind of switching requires electromechanical or transistor based relays.

My choice is relays based switching only because of the remote control. 

The electromechanical relays have very simple control, low resistance, slow switching times (millisecond range), limited mechanical life and suffer from thermal EMF effect due different materials used. Of course there are low thermal EMF reed relays like Pickering series 100 with <1 uV and Coto series 3500/3600 with 0.5-10 uV. Unfortunately the low thermal EMF reed relays are expensive and some of them can be purchased only from the manufacturer.

The transistor based relays (JFET/MOSFET/BJT) are very fast (nanoseconds range), needs more complex control, have low thermal EMF, they are cheap and can be purchased from electronics distributors.

Here I selected the JFET based switch because of the lowest noise and the low EMF among the other possibilities.

Of course there are some drawback when JFET transistors are used:
- Voltage offset error due reverse gate-source leakage (Igss). Additionally this parameter is temperature sensitive: roughly doubling every 10°C.
- Glitches (signal transients) during switch on/off due charge injection.
- Normally closed (the switch is turn on by default).
- Control logic is more complex.

Igss is the most important parameter when JFET switch is used for mode selection. When the switch is closed, the value of the Igss multiplied by the input resistance of the circuit under the measurement, will generate voltage error offset. For example, if the Igss is 1pA and circuit resistance is 1MOhms, the voltage offset of 1uV will be generated.

There are not too much JFET transistors, which have Igss in the pA range. Vishay company produced before 2017 the 2N4117A with maximum Igss value of 1pA and typical value of 0.2pA for 25°C. The price was between 4 and 9 USD. The next best transistor, which is currently available on the market, is the MMBF4117 (N-channel) made by On Semiconductor with maximum 10pA Igss for 25°C and price below 0.5 USD.

During JFET search, I found one interesting document from TI for op amp over voltage protection, using JFET as diode (drain and source connected). Later I tried on the breadboard and it was working fine. So, now I think to use this approach for protection of the first op amp, which make unnecessary the +/- 30 V power supply in my post about the initial schematics for the low accuracy voltmeter.

So, back to schematic. Using JFET transistor as switch, needs some extra components when the TTL compatible control logic is used. The N-channel JFET transistor is open (turn off) when the negative voltage applied between Gate and Source is greater than Vgs(off) parameter value of the transistor and more negative than the input signal voltage level. In the case of MMBF4117, the Vgs(off) parameter have maximum value of -1.8V.
The control logic (micro-controller/CPLD/FPGA) usually use TTL levels, so it is better to use analog comparator to drive the JFET transistor. The positive Vcc can be set to 20V and negative should be greater than expected input voltage. In my case this will be -20V. The maximum output current of the comparator must not exceed maximum value of the JFET's  forward gate current.

JFET SPST switch

The final picture of DMM mode selection is shown below. The ohm meter schematics is based on the Linear technology's LTC6081/LTC6082 datasheet, page 14. The following switches are used in the resistance measurement:
- switch "SW VRef" for extending Ohm-meter ranges, when high resistance is measured using 10 times smaller voltage reference. 
- switch "SW FB4W" will be used in 4 wire resistance measurement. In this mode reference resistor "Rref 4W" with value 1K will be used.
- switches "SW FB2W" and "SW 2W" will be used in 2 wire resistance measurement. In this mode reference resistor "Rref 2W" with value 100K will be used. 
Calibration of the resistance measurement will be external for low accuracy and internal for high accuracy version of the DMM. I will use the Vishay H series (VHP202) resistors as secondary resistance standard. According datasheet, the shelf life is 2ppm for 6 years and maximum TCR is 2.5ppm/°C

When voltage is measured, all switches will be switched off and the "SW VM" will be switched on.
When current is measured, all switches will be switched off and the "SW CM" will be switched on.

The switches "SW VM" and "SW CM" are placed after the input buffer to decrease the leakage of the JFET in the front of the input buffer. The output of the buffer is low resistance and the error due these 2 switches can be ignored.

The total leakage in the 2W/V binding post (BP), before the input buffer, will be sum of Igss of the "SW 2W", over voltage protection JFETs and the Ibias of the input buffer. Using MMBF4117 and LTC2057, this means maximum ~ 3*10pA + 200pA = 230pA for 25°C. For comparison the high end DMM like Keithley has <100pA leakage by specification.

It is hard to find low noise, low Ibias, zero-drift and high-voltage op-amp. One alternative is using the LTC1050/1052, which have 30pA maximum Ibias, 0.5/1.5uV LF noise at 1Hz/10Hz and maximum 5uV Vos. The only problem is the low supply voltage of 18V. This can be resolved using bootstrapping technique described in the www.edn.com site.

The status of every JFET switch when particular measurement is performed is given below:

Measurement	SW VM	SW CM	SW 2W	SW FB2W	SW FB4W
Voltage	CLOSED	OPEN	OPEN	OPEN	OPEN
Current	OPEN	CLOSED	OPEN	OPEN	OPEN
Resistance 2W	CLOSED	OPEN	CLOSED	CLOSED	OPEN
Resistance 4W	CLOSED	OPEN	OPEN	OPEN	CLOSED

Update 2 May 2018 : Added a diode between the comparator output and the Gate of the JFET switch. The reason is described at the end of the part 2.

Update 5 June 2019 : I found better way to measure resistance using stable reference resistor and stable, but not precise current source. The current source is applied across the reference resistor and goes through the resistor under test. The voltage drop over the reference resistor will be used as reference voltage of the ADC. By this way the resistance is measured as ration between the resistor under test and the reference resistor. The only thing which I have to realize is switching between the LTC6655 and the reference resistor in front of the LTC2440.  This idea I got during making the digital thermometer using ADS1220 IC..