Following the previous post, I made experiments with JFET switches in single-pole dual-throw configuration. This kind of switches are used in 3 places: switching between voltage and current meters, 2W/4W input of the ohm-meter feedback schematics and in the voltage reference selection switch.
The problem with SPDT configuration using the JFET transistors is the glitches when switching between the two voltage sources. The only instrument which can be used for resolving this issue is oscilloscope, which I did not have until recently. Last 6 months I looking for low cost oscilloscope and finally bought the new Siglent SDS1202X-E :
It is very compact, 2 channel, 200MHz/1GSps oscilloscope with RS232/I2C/SPI/LIN/CAN free decoding options.
The goal of this experiment is to create glitch free SPDT switch using 2 JFET transistor J109 from OnSemi which I had. The SPDT switch connects at one moment only one of it's dual input:
To make this possible, two JFET transistor should be connected together at the Source pin, their Drain pins will be connected to the input voltages. At one time only one of the transistor will be open and the another will be closed. This is realized with signals in opposite direction (logical 1 and 0) which feed the comparators connected to the JFET gates. The positive power supply of the comparators is +15V and the negative is -15V.
Lets start with the push button which will switch between two inputs. I'm using the classic debounce circuit with RC in front of inverting schmitt trigger:
The channel 1 of the scope is connected before the schmitt trigger and channel 2 is connected after it. The scope clear shows that rise time after the RC is around 37 ms, but the signal after the schmitt trigger decrease it to 1.2us.
Next step is to generate two opposite signals every time when the push button is pressed. I will use one more inverter to produce this opposite signal:
No more glitches and about 130 ns fall time from +5V to -5V.
But when I looked into the transition from -5V to +5V, there are a still lot of glitches:
After increasing the pull-up resistor with 5K, the transition is much better, but still there is small glitch:
And finally after adding small 20pF capacitor between the gate and the ground, the result is much better:
The transition time is increased about 3 times, but the transition glitch is gone.
So the learned lesson is that glitches depends on comparator's positive power supply voltage, pull-up resistors and compensated capacitor between the gate and the ground. Probably using different JFET transistors will change transition picture as well, so the only way is to use always a scope to check for glitches.
Update 2 May 2018: This post was mainly dedicated to removing glitches during switching, but I never check with high resolution DMM if the output voltage is the same as the input one. At the time of writing this post I had only my 3.5 digits KEW 1012 DMM and there was no differences between output and input voltage. However, recently I made the same schematics for my mutli-voltage reference calibration PCB and found that there are several hundreds micro-volts difference measuring with 6.5 digits DMM. After playing with the LTSpice, the problem was resolved with adding a diode between the comparator output and the JFET gate and confirmed with the real measurement. Note that the diode must have minimal reserve current leakage or it is better to use JFET with Igss in the pA range as diode (shorting the Drain and the Source as catode and the Gate as anode).
It is very compact, 2 channel, 200MHz/1GSps oscilloscope with RS232/I2C/SPI/LIN/CAN free decoding options.
The goal of this experiment is to create glitch free SPDT switch using 2 JFET transistor J109 from OnSemi which I had. The SPDT switch connects at one moment only one of it's dual input:
Lets start with the push button which will switch between two inputs. I'm using the classic debounce circuit with RC in front of inverting schmitt trigger:
The channel 1 of the scope is connected before the schmitt trigger and channel 2 is connected after it. The scope clear shows that rise time after the RC is around 37 ms, but the signal after the schmitt trigger decrease it to 1.2us.
Next step is to generate two opposite signals every time when the push button is pressed. I will use one more inverter to produce this opposite signal:
In the scope, the first channel shows the signal after the inverter and the second channel shows the signal before the inverter.
Now I have to connect the opposite signals to the input of comparators and to look what will be shown in the output. The used comparator is LM393P with 10K pull-up resistors. The minus input of the comparators are connected to resistor divider which provided 1.5V threshold voltage.
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| Full schematics (see the update at the end of the post regarding the diodes) |
The output from the connected JFET transistors is 5V when the button is not pressed and -5V when it is pressed:
If we zoom in to see the transition period we can see the following picture:
When the input voltage is going from +5 to -5V, there are glitches around the -5V with 4V peak to peak value.
If the positive supply of the comparators is decreased to +5V instead using +15V, the transition is much better:
But when I looked into the transition from -5V to +5V, there are a still lot of glitches:
After increasing the pull-up resistor with 5K, the transition is much better, but still there is small glitch:
And finally after adding small 20pF capacitor between the gate and the ground, the result is much better:
The transition time is increased about 3 times, but the transition glitch is gone.
So the learned lesson is that glitches depends on comparator's positive power supply voltage, pull-up resistors and compensated capacitor between the gate and the ground. Probably using different JFET transistors will change transition picture as well, so the only way is to use always a scope to check for glitches.
Update 2 May 2018: This post was mainly dedicated to removing glitches during switching, but I never check with high resolution DMM if the output voltage is the same as the input one. At the time of writing this post I had only my 3.5 digits KEW 1012 DMM and there was no differences between output and input voltage. However, recently I made the same schematics for my mutli-voltage reference calibration PCB and found that there are several hundreds micro-volts difference measuring with 6.5 digits DMM. After playing with the LTSpice, the problem was resolved with adding a diode between the comparator output and the JFET gate and confirmed with the real measurement. Note that the diode must have minimal reserve current leakage or it is better to use JFET with Igss in the pA range as diode (shorting the Drain and the Source as catode and the Gate as anode).
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