Temperature coefficient and the humidity effect on the LTC6655 voltage output

Between the 11 April and 14 May 2020 I tried to measure the 1 month stability of the LTC6655. During this period I made 80 measurements and the result is shown in the following chart:

Stat	RH %	Tamb °C	V ref, V
Min	24	19.8	2.5003369
Max	54	26.6	2.5003616
Peak to Peak	30	6.8	0.0000247
ppm	0.33ppm/%RH	1.45ppm/°C	9.88ppm

Based on the statistic data, the temperature coefficient was 1.45 ppm/°C and the dependency from humidity was 0.33ppm/%RH. The TC for LTC6655B was below the 2ppm/°C. There is no explicitly given value for the humidity's effect on the voltage output, but was mention that "... humidity sensitivity can be reduced to less than 35ppm for a change in relative humidity of approximately 60%." if PCB slots cuts are made around the LTC6655. This is equal to 0.58ppm/%RH. Because I used small MS8 adapter, I thought that the measured value corresponds to the datasheet value.

However, looking into the chart it is visible that the output voltage is affected more by humidity than by temperature. So I tried to extract measurement data, where the fluctuation of the temperature is relative small and got the next chart, where the dependency is more clear:

According the datasheet, only the LS8 package is not affected by the humidity. I have one LS8, but I do not have PCB to solder on it. So the only option to see what is the real temperature coefficient is to insulate with Fibran XPS the box where the LTC6655 is placed and to fill it with several silica gel packages. This would allow me to keep the humidity in very narrow range.

For period of 12 hours, I was able to keep the relative humidity inside the box in the range of 0.9%, while the external humidity was in the range of 6.87%. The relative humidity and temperature measurements were performed with pair of BME 280 sensors. The result of the measurements are shown in the chart below. It is clearly shows now that the dependency between the temperature in the box and the voltage output is linear. The measured voltage deviation was 5.32ppm for 2.8 °C difference, which makes 1.9ppm/°C within the datasheet specification. 

I wanted to make the same experiment for longer period of time, so the silica gel bags were baked into the oven for about 3 hours in 100°C. In the next 6 days, after 23 measurements, the humidity in the box was changed with 4.3% RH (0.72% per 24h) which is about 3 times better compared to the previous time. The temperature coefficient was not changed so much from the previous time: 1.89ppm/°C for 4.36°C temperature range.

Here an idea popped into my head : if this linearity can be proved for the +/- 5°C and there is no hysteresis within this interval, it would be possible to characterize the LTC6655 for this range and to use the data for an artificial calibration like the HP 3458a and the Advantest R6581 multi-meters. But for that, I have to make PCB for the LS8 package and to make temperature controlled camera.

Revised analog front-end : Replacing the analog switch, part 4/4

In the post for the automatic voltage range, I used the analog switch ADG5419 to switch between the low and the high voltage ranges. I was wondering if the switch can be replaced with the shutdown feature of the LTC2057 op-amp. According the datasheet when the LTC2057 is in the shutdown mode : "... the output presents a high impedance to external circuitry". If the outputs of the op-amps are shorted and the SD inputs are feed with opposite signals for each op-amp, in theory this is equivalent to a SPDT switch. The switch is not expensive one (it cost around 5USD), but the maximum voltage which can stand (+/- 22V) was less than the voltage which I will use for the LTC2057HV. So usage of the ADG5419 cost me 2 more power rails which I want to avoid.

Тhis raised the following question : what kind of glue logic ("A" in the schematics above) I have to put between the outputs of the MAX990  comparators and the SD/SDCOM op-amp inputs? 

The output pin of the MAX990 is an open drain and a pull-up resistor to the positive rail have to be added. The voltage outputs of the MAX990 are between -2.5V+Vds(of the open-drain stage) when input voltage is above 2.048V and +2.5V when input voltage is below 2.048V.

From the LTC2057 datasheet we have the following information: "Shutdown control is accomplished through differential signaling. This method allows for low voltage digital control logic to operate independently of the amplifier’s high voltage supply rails.". And the tables with the logic and operating voltage ranges:

From the operating voltage range we had the restriction that voltage between the SD and SDCOM must be no more than 5.4V and it should be between the op-amp's power rails (except for the SDCOM max value). This was fine as far as the MAX990 outputs are between -2.5V and +2.5V. If the SDCOM is connected to the -2.5V power rail, I need two opposite signals from the MAX990 outputs which to be connected to the SD pins. 

I thought : why not to put an NOR gate 74x logic? The negative input voltage is not a problem if the Vss is connected to the -2.5V power rail and the Vcc is connected to the +2.5V. So, I made a breadboard proof of concept and putting the scope probe on the shorted outputs of the LTC2057 op-amps, I got a very clean, 2 us transition time between the two input signals.

Revised analog front-end : Over Voltage Protection, part 3/4

This post will focus on a practical selection of over-voltage protection components, their parameters, schematics and needed calculations. The tests' results are given at the end.

The standard over-voltage protection in the 3-4 digits handheld digital multimeters is build with a current limiting PTC, placed in series and voltage spike suppressor MOV, which is placed in parallel to the input buffer. When we are talking about 6+ digits DMM, this solution is not suitable due to the high current leakage of the PTC and the high resistance, current leakage and capacitance of the MOV.

For voltage protection up to 100V DC, ultra-low leakage diodes or JFET transistors can be used. For higher voltages, I think a Gas Discharge Tube (GDT) can be used due to their absent of the current leakage.

How over-voltage protection works

When the input voltage is greater than the positive (or less than the negative) voltage rail and the forward diode voltage, the diode will begin to conduct and the current will pass from the limiting resistor through the diode to the positive or negative power rail. The positive rail must sink the current and the negative rail must source the current.

There is one problem: when a standard LDO is used for positive rail, it can not sink a current. As a result, the current through the diode will increase the voltage on the positive rail and can damage the circuit under the protection.

There are two solutions to this problem: to use a buffer op-amp which can sink between several to tens mA or to use schematics I found during the op-amp selection from the ADA4177 datasheet - an PNP transistor which "re-routes" the current from the diode to the "sinking" ground. I tried the solution in the ADA4177 and it works perfectly.

If a dual-polarity power supply is used for the op-amp, the negative power rail will source the current through the diode and the voltage will not be increased when the input voltage exceeds the negative power rail.

The maximum input voltage is the sum of the power supply voltage and the continuous reverse voltage that can withstand the diode. The input voltage for the op-amp will be clamped to the following values:
- For the positive over-voltage: the sum of the positive power rail voltage, the diode's forward voltage and the base-emitter voltage of the PNP transistor.
- For the negative over-voltage: the sum of the positive power rail voltage and the forward voltage of the diode.

The clamping voltage must not exceed the maximum allowed power supply of the op-amp. Let's give one example with LTC2057HV that has spec of 60V supply peak to peak voltage (65V absolute maximum). If the op-amp is supplied with +/- 27V, this will give 60V-(2*27V)=6V maximum clamp above the positive or negative power rail. That means that maximum allowed value is +/-33V.

Component Selection

On the market there aren't so many diodes that have pA range leakage current. The few of them are: BAV199, BAS416 and PAD series diodes with guaranteed maximum values, but they are very expensive. The alternative is a JFET transistor like MMBF4117 with shortened drain and source pins.

Which parameters should you look at? Here is the list:

- "Reverse/leakage current" for diodes or "Gate to Source Reverse Current (IGSS)" for JFET transistors. The value should be in pA range, preferably less than 10pA.

- "Continuous reverse voltage" for diodes or "Gate to Source Breakdown Voltage (V(BR)GSS)" for JFET transistors. The value should be as high as possible.

- "Continuous forward current (IF)" for diodes or "Continuous Forward Gate Current (IFG)" for JFET transistors. This is the maximum current which has to be limited by a serial resistor.

The maximum reverse voltage that can be applied is the power supply voltage and the maximum value of the diode's continuous reverse voltage. The current which will flow through the resistor and the diode is:

I limit = (Vin - (Vsupply + Vfwd + Vpnp*))/Rlimit

Where:

- Vin is the input voltage.

- Vsupply is the voltage on the power supply rail.

- Vfwd is the forward voltage of the protection diode.

- Vpnp is the optional base-emitter voltage if positive sink schematics is used.

- Rlimit is the value of the limiting resistor.

The limit current value must not exceed the maximum value of the diode's continuous forward current and the resistor's power rating has to be selected based on the current and the resistance.

The table below shows calculated data for the dual diode BAV199, the single diode BAS416 and the JFET transistor MMBFF4117. Two values of the limiting resistors are given - 2K and 10K.

	BAV199/BAS416	MMBF4117	BAV199/BAS416	MMBF4117
V supply, V	27	27	27	27
Max reverse voltage, V	75	40	75	40
Max protection, V	102	67	102	67
Max current, mA	160/200	50	160/200	50
Limit resistor, Ohms	2000	2000	10000	10000
Limit current, mA	23.5	6.0	4.7	1.2
Limit Resistor Power, W	1.105	0.072	0.221	0.014
Noise, RMS uV 1pA/√Hz	0.01	0.01	0.03	0.03
Leakage voltage (100pA), uV	0.20	0.20	1.00	1.00

Calculated values of noise and leakage voltage are shown in the last two rows in the table. 

The RMS noise value is calculated based on relative high current noise density of 1pA/√Hz. Even with 10K limiting resistor, the noise is low and can be ignored. 

However, the error due to current leakage of the whole front end which includes the reverse current of diodes and the input buffer can be significant. In the table, calculation shows that for 100pA total leakage which was my total error budget, the voltage error can be between 0.2 and 1uV respectively for 2K and 10K resistor. On the 1V range, this makes 0.2-1.0 ppm error.

The small value of the limit resistor is preferably, but this will increase the current. Maybe the 2K resistor is a good trade-off: the maximum error due to leakage  of 100pA is 0.2uV and the resistor power is around 1W for the BAV199/BAS416.

The test

The PCB made for the op-amp test from the previous post was used for the test. I soldered two JFET MMBF4117 transistors for the over-voltage protection. The limiting resistor was 5K (2x10K in parallel). For the test with the current sink, I added an external PNP transistor and a diode.

Additional circuits for the current sink.

I used two PSU:

- A small, custom made PSU which contains a Digital DC-DC Ruideng DPS 3003 with voltage range of 0-32V and two regulated LDO in the range of -/+ 1.3V to 30V. The DC-DC converter and the both LDO share same common ground.

- Analog HP 6237B PSU with dual polarity outputs +/- 23V and one single 18V output.  

 

Since I do not have high voltage PSU, I had to set the power supply to much lower values +/- 2V and apply up to 32V input voltage.  

Positive over-voltage test description:

- The power supply rails were set to +/- 2V using the LDOs
- The input voltage was set from 0 to 32V with 1V step using the DPS 3003

- The following voltages and current I was monitoring: the positive rail V+ (Advantest R6581T), the clamp voltage Vclamp (HP 34401A), the input current through the limiting resistor I limit (Kyoritsu KEW 1012)

- The test was made two times: once with sink current circuits and without it.

Test without the current sink circuit.

Test with the current sink circuit.

The pictures show when the current sink circuit is used, the current which flows through the diode and goes to the common ground. This is visible in the current measurement of the DPS 3003. When the current sink circuit is not used, the current is "missing" on the DPS 3003 display, but the KEW 1012 multimeter shows that it actually exists.  The test results show, that this extra current is the reason for increasing positive power rail. 

And here are results from the test:

The red solid line is voltage on the positive power rail with current sink circuit. The voltage was stable at 2V during the whole ramp-up. 

However, if we look into the blue solid line (without current sink), we can see during ramp-up of the input voltage went from 21 to 32V, the positive power supply was increased from 2V to 2.7V. The dependency is very linear and will be further increased if we continue to rump-up.

The same linear increasing of the voltage is observed for the voltage clamp when the current sink circuits is not used (the blue dash line). However, the red dash line which is the voltage clamping value with current sink circuit shows stable value across 21-32V range. 

Using linear regression, I can estimate increasing the voltage clamp up to 4V for 40V input voltage and up to 6.3V for 75V input voltage when current sink circuit is not used. This can destroy the op-amp if there is not enough head-room of the power supply.

There is no difference in the current passes through the resistor and the diode. This is visible with the blue and red dot lines. 

Negative over-voltage test description:

- The power supply rails were set up to +/- 2V using the HP 6237B PSU.
- The input voltage was set from 2 to -30V with 1V step using the negative LDO.

- The following voltages and current were monitored: the negative rail V- (Advantest R6581T), the clamp voltage Vclamp (HP 34401A), the current through the limiting resistor I limit (Kyoritsu KEW 1012).

Here the negative power rail voltage is constant during the input voltage ramp-up. The clamp voltage is also relative constant after input voltage exceeds the power rail and diode's forward voltage.

Update 15 April 2021:

I got a mail from blog's reader with a link to Maxim's Application Note 4035 about "Overvoltage protection for sensitive amplifier applications". The interesting part is "Differential Diode Protection".

Revised analog front-end : op-amp selection and test, part 2/4

In this post I want to find out if a single buffer op-amp can replace the classic schematics used in the old days of DMM. I tested some parameters which are critical for the analog front-end. Some of them are given only as typical values and I want to know what is maximum value I can expect.

Based on the available schematics of old DMM (HP/Agilent 34401A, 34420A, 3458A, Datron 1281/1271, Keithley 2001), we can see that a pair of  JFET in common source or source follower circuit are used in front of the main buffer op-amp. This is because back then a single op-amp that can satisfy all criteria for error budget, was not available. Mainly these errors are related to input bias current and noise. For example the HP 34401 uses the OP-27GS op-amp which has very high bias current and current noise density. To solve this problem, a matched J-FET source-follower pair (NPDSU406) was used in front of the OP-27GS. This produces other problems which were resolved with additional circuits. More information can be found in the book "The Art of Electronics". I want to avoid this complexity, so I can find if newer op-amps are good enough. 

The only exception I found was the Keithley 2000 model where LTC1050C op-amp is used in bootstrap schematics. This allows the rated for maximum +/- 9V supply operation op-amp to be used for input signals up to +/- 12V (20% over range for the 10V range).

Selection of op-amps

In the previous post I made error budget for op-amp parameters and now I have to select available op-amps on the market. I made 3 groups of them : 

• op-amps capable to handle input signals up to +/- 22V full scale range.
• op-amps capable to handle input signals up to +/- 12V full scale range.
• op-amps with errors below my threshold, but with maximum power supply under 10V. Using bootstrap schematics they can be used for input signals up to 22V. It's kind of a back-up plan if the previous 2 group failed.

After few weeks of looking for available op-amps and collecting parameter values, I selected 3 op-amps for the first group : LTC2057HV, ADA4522, MCP6V51 and 3 in the second group : OPA140, OPA192, LT1024A and 5 in the last group : ADA4530, ICL7652, LTC1052C, TLC2654AC, OPA376. 

Additionally I added the OP-27GS and LTC1050C as comparison to the selected op-amps.

In the tables below, the parameters are sorted by my priority given in the first column. All values which do not fit in my error budgets are colored in red.
The error budget is:

• Ibias less then 50pA
• Voltage noise, p2p value less than 4.4uV for the 22V range and less than 2.4uV for the 12V range. This is equivalent to 7 digits. The test for this parameter will be performed with short between positive input and the ground. 
• Current noise density, RMS value less than 1041 fA/√Hz for 22V Range and 557 fA/√Hz for 12V Range. My criteria for this threshold is to reach a 6 digits when the input resistance is 1MOmhs and take into account the previous voltage noise thresholds.
• Estimated Effective Number Of Digits (ENOD) for 99.7% probability. Combining voltage noise, current noise density and the input resistance must provide at least 6 digits for 12V or 22V ranges when input resistance is 1MOhms or at least 7 digits when the inputs are short. The used formula is:

        ENOD = Log10( FS/NoiseP2P)

        Where:

         - FS in Volts is the full scale for the range including the over-range. In the case of the 10V range, 12V over-range, the value is 24V and in the case of the 20V range, 22V over-range, the value is 44V.

           -  NoiseP2P in Volts is the peak to peak noise calculated by the following formula:

          NoiseP2P = 6.6 * SQRT (VnoiseRMS²+(InoiseRMS*Rin)²+RinNoiseRMS²)

          

         VnoiseRMS is the RMS value of the input noise voltage spectral density for 10Hz bandwidth. If only the peak to peak value is given for 10Hz bandwidth, VnoiseRMS = Vnoise p2p / 6.6.

          InoiseRMS is the RMS value of the input noise current spectral density for 10Hz bandwidth.

          RinNoiseRMS is the RMS value of the resistor thermal noise for 10Hz bandwidth, which is 0.41uV for 1MOhms.   

• Input Voltage offset (by temperature, by time and initial value) : less than 1uV/°C and less than 1uV per month none cumulative. The initial value is not so important because it will be calibrated anyway.
• Input resistance of the op-amp : at least 100GOhm
• CMRR : minimum 120dB

	Voltage Range, V	22			12			12	12
	Manufacturer	LT/AD	AD	Microchip	TI	TI	LT/AD	Agilent 34401	Keithley 2000
Prio	Parameter ↓ / Op-amp ->	LTC2057HV	ADA4522	MCP6V51	OPA140	OPA192	LT1024A	OP-27GS	LTC1050C
1	IBias, typ pA	30	50	60	0.5	5	25	15000	20
	IBias, max pA	200	150	250	10	20	120	80000	125
2	Voltage Noise p2p, typ uV	0.22	0.117	0.21	0.25	1.3	0.5	0.09	1.6
2	Current Noise RMS fA/√Hz	130	1100	4	0.8	1.5	20	600	1.8
	Est. p2p noise Rin=1MOhm, uV	3.84	23.10	2.72	2.72	3.00	2.78
2	Est. ENOD Rin=1MOHms	7.06	6.28	7.21	6.95	6.90	6.94
2	Est. ENOD Rin=0Ohms	8.30	8.58	8.32	8.25	7.53	7.94
3	Vos Tdrift, typ uV/C	N.A.	0.006	0.005	0.35	0.1	0.25	0.4	0.01
3	Vos Tdrift, max uV/C	0.025	0.03	0.031	1	0.5	1.5	1.8	0.05
3	Vos long-term month uV	near zero	near zero	2	N.A.	N.A.	0.3	2	0.05
	Vos, typ uV	0.5	1.5	2.4	30	-/+ 5	15	55	0.5
	Vos, max uV	5	7	15	120	-/+ 25	50	200	5
4	Rin, GOhms	N/A	1000	120	10000	10000	2000	2	N/A
5	CMRR, min dB	133	140	135	126	120	112	100	114
	Vsupply max V	-/+30	-/+27.5	-/+24.75	-/+18	-/+18	-/+20	-/+22	-/+9
	Price, USD w/o tax, Mouser	5.29	2.68	1.32	3.61	2.68	16.07	3.56	5.78

Details in the datasheet should be read carefully, because they are not always obvious. For example :

• In the LTC2057 datasheet, the input noise current spectral density for +/- 30V is specified as 130 fA/√Hz, but later it's stated that "The DC average of injection current is the specified input bias current, but this current has a frequency component at the chopping frequency as well. When these small current pulses, typically about 0.7nA RMS, interact with source impedances or gain setting resistors, the resulting voltage spikes are amplified by the closed loop gain". I never got the value of 130 fA/√Hz with 1MOhms input resistance, but the measurements were close to the mentioned 0.7nA.

• In the ADA4522 datasheet, the current noise density for 55V is specified as 800 fA/√Hz, but for a gain of 100. Later in Figure 78 for a gain of 1, voltage supply of +/- 27.5V and input resistance of 100KOhms, the current noise density is about 1100 fA/√Hz for 10Hz-1KHz bandwidth.

	Voltage Range with bootstrap, V	22
	Manufacturer	AD	TI	LT/AD	TI	TI
Prio	Parameter ↓ / Op-amp ->	ADA4530	ICL7652	LTC1052C	TLC2654AC	OPA376
1	IBias, typ pA	0.001	4	1	50	0.2
	IBias, max pA	0.02	30	30	60	10
2	Voltage Noise p2p, typ uV	4	2.8	1.5	1.5	0.8
2	Current Noise RMS fA/√Hz	0.07	4	0.6	4	2
	Est. p2p noise Rin=1MOhm, uV	4.83	3.89	3.09	3.10	2.82
2	Est. ENOD Rin=1 MOHms	6.70	6.79	6.89	6.89	6.93
2	Est. ENOD Rin=0 Ohms	7.04	7.20	7.47	7.47	7.74
3	Vos Tdrift, typ uV/C	0.13	0.003	0.01	0.01	0.26
3	Vos Tdrift, max uV/C	0.5	0.05	0.05	0.05	1
3	Vos long-term month uV	~1.5	0.06	0.1	0.02	N.A.
	Vos, typ uV	9	0.6	0.5	4	5
	Vos, max uV	50	5	5	10	25
4	Rin, GOhms	> 100000	N/A	N/A	N/A	N/A
5	CMRR, min dB	110	110	120	110	76
	Vsupply max V	-/+8	-/+8	-/+8	-/+8	-/+2.5
	Price, USD wo tax	23.47	6.09	8.77	5.92	1.69

I bought 2 pcs. LTC2057HV in SOIC-8 package and I had previously one in MSOP-8 package, 2 pcs. ADA4522 in SOIC-8 package and 3 pcs. MCP6V51I in MSOP-8 package (one of which I accidentally damaged with reverse supply polarity):

Description of the tests

Using the 8.5 digits Advanttest R6581T DMM I will do the following tests for the selected op-amps :

• Ibias with 1MOhm resistor connected between the positive input and the ground.

• RMS and peak to peak noise with 1MOhms input resistance.

• RMS and peak to peak noise with short inputs.

• Vos with short inputs.

• Measuring voltage difference between input and output voltage vs. variations in the input voltage. I call this kind as linearity. In ideal case the differences between the input and output voltage of unity gain op-amp must not depend on changes of the input voltage and this difference must be constant.  The measurement value is equal to (Max(∆(Vout-Vin)) / ∆Vin) * 1E+6 (ppm).

To do these tests, I made a small PCB for above tests plus possibility to measure the leakage of over-voltage protection JFET. Later I realized that it is not the perfect PCB and the second version is already developed, but I have to wait for the end of the current world pandemic situation. In the first PCB version I forgot :

• the bypass capacitors, so I have to solder them at the back of the PCB near to  the supply pins. Without them the results are really scrappy.
• to add guard ring around the input positive terminal of the op-amp. This is a recommendation found in the datasheets for current leakage limitation. 
• the possibility to disconnect the 1MOhms resistor from the ground that is required for the linearity test.  
• the load resistor between the op-amp output and the ground.

Additionally I added OVP with double diodes (for BV199) in SOT23 package, feedback resistor required for some op-amps. Here is the layout of the second PCB version:

Other tests which can be made, but I do not have proper equipment or the time for that:

- IBias vs. Vcm using Source Meter Unit. This characterization test can be seen in many datasheets. Unfortunately I do not have such equipment, therefore I can't make a test. I looked for low-cost solution and I found an evaluation board of AD5560 parametric measurement unit, but the lowest range was 5uV that required external 24 bit ADC to make pA measurements. The proper SMU like Keithley 236 is capable to measure down to pA range, but it is still in the 1300 - 2000 USD price range in EBey without shipping and VAT. 

- Vos vs. Temp using thermo-regulated chamber.
- Vos long term drift.

Here are the pictures for the first version of the test PCB which I order from OSHPark. When op-amp is in the MSOP-8 package I solder it on the breakout board and PTFE cables are used to connect to the main test PCB: 

Results from the tests

First I made noise tests with short input and 1 MOhms resistor for the R6581 and HP 34401 as reference. The conditions were: 10V Range, Hi-Imp mode, AZero On, 100 NPLC, 50 samples.

	R6581		HP 34401		Keitley 2000		Keitley 2002
	STDEV, uV	P2P, uV	STDEV, uV	P2P, uV	STDEV, uV	P2P, uV	STDEV, uV	P2P, uV
Vnoise Zero	0.06-0.106	0.2-0.3	0.48-0.6	2-2.5	0.834-0.88	3.44-4	0.598-0.734	2.92-3.37
ENOD Zero	8.3-8.05	8.08-7.9	7.4-7.3	7.08-6.98	7.16-7.13	6.8-6.77	7.56-7.47	7.17-7.11
Vnoise 1M	0.197-0.347	1-2.7	0.514-0.714	2.1-3.5	2.38-3.64	10-20	1.58-1.95	26.13-28.95
ENOD 1M	7.78-7.53	7.38-6.95	7.36-7.23	7.06-6.83	6.7-6.5	6.38-6.07	7.14-7.05	6.22-6.18

I made more than 20 measurements with 50 samples each for the R6581 and HP 34401 and 2 measurements with 50 samples for the rest of the DMM. In the table it's shown the minimum and maximum values of the STDEV, peak to peak values in microvolts and respective ENOD values. You can see from the data, that R6581T and Keithley 2002 lost one digit when 1MOhms resistor was attached to the op-amp's input. On the other hand, the HP 34401A keeps very closely to the 7 digits even with input 1MOhms resistance: the average ENOD from 20+ measurements was 6.93.

The next table shows the tests for the following parameters: Vos, Ibias, Linearity, Voltage RMS and peak to peak noise when inputs are shortened and when 1MOhms input resistor is used. 

The first few bias current measurements of the MCP6V51 where far away from the specification limits (5.5nA bias current) so I decided to skip the rest of the tests. Because it was hard to solder and de-solder other MSOP-8 op-amps (I damage tracks on one of the test PCB) I skipped tests for the second MCP6V51 too. And decided to keep testing the third LTC2057HV which was in MSOP-8 package.

Results with test board ver. 1	Package	Vos, uV	Ib, pA min- max	Ib, pA max spec	Linearity, ppm Rout = open	Linearity, ppm Rout=10K	Noise, uV
							Zero, STDEV	Zero, p2p	1M, STDEV	1M, p2p
LTC2057HV 1	soic-8	3 - 6	53.66 - 62.19	200	0.491	1.291	0.107 - 0.159	0.4 - 0.7	1.257 - 1.97	5.73 - 9
LTC2057HV 2	soic-8	0.9 - 7.2	688 - 736	200	0.473	1.214	0.113 - 0.201	0.4 - 0.9	1.767 - 7.65	6.4 - 34.4
LTC2057HV 3	msop-8	5.4 - 7	12.9 - 33.5	200	N.A.	N.A.	0.117 - 0.230	0.5 - 1.1	1.59 - 2.62	7.2 - 11.8
ADA4522 1	soic-8	-0.2 - 0.3	1002.4 - 1004.7	150	0.055	0.059	0.128 - 0.118	0.4 - 0.6	1.63 - 5.44	6.7 - 30
ADA4522 2	soic-8	0.8 - 1.8	692 - 695	150	0.1	0.036	0.112 - 0.243	0.6 - 0.8	3.26 - 10.7	15.8 - 43.8
MCP6V51I 1	msop-8	-0.2 - -0.3	5502 - 5510	250	N.A.

The only op-amp which passed the bias current tests was the third sample in msop-8 package. The first one was very close to the 50 pA limit. The second sample was 3-4 times above the specification limit. The rest of the op-amps failed as well.

All LTC2057HV and ADA4522 passed the noise tests with 7 digits ENOD for short input test and 6 digits ENOD for 1MOhms input resistor.

Linearity results were under 1ppm for LTC2057HV and ADA4522 when the output is not loaded, but when 10K load resistor is connected, the linearity cross the threshold of 1ppm for the LTC2057HV. Probably the reason is the missing sense connection from the op-amp output to the resistor and the voltage drop over the resistor leads can worse the linearity measurements. I already made correction in the test PCB ver.2 and if this does not help, I have to use a current buffer like in my LTZ1000 voltage reference to resolve this issue.

Based on my initial tests, I can answer to my question in the beginning of this post: single buffer op-amp solution as front-end is feasible, but test of the buffer op-amp is required. Relaying only to typical or even maximum parameter's values in the datasheet is not enough.

This post is still in progress. Once I get the test PCB ver. 2, I will buy more op-amps and will do a second try.