This is the beginning of a 4 part post about revising the analog front-end of the Voltmeter. It is based on gained calibration knowledge and the new collected information during the last 2 years:
Part 1: Identifying possible errors in the analog front-end.
Part 2: Selection and characterization of the input buffer op-amp. Here I will check if a single op-amp solution can be found with newer op-amps available in the market.
Part 3: Over-voltage protection.
Part 4: Replacing the analog switch in initial design with a shut-down feature of the LTC2057 op-amp.
If a single input buffer op-amp solution can't be found in part 2, I will have to test the classical source follower, the common source differential amplifier and/or the bootstrap schematics. Eventually this will come as an additional 5th part.
Part 2: Selection and characterization of the input buffer op-amp. Here I will check if a single op-amp solution can be found with newer op-amps available in the market.
Part 3: Over-voltage protection.
Part 4: Replacing the analog switch in initial design with a shut-down feature of the LTC2057 op-amp.
If a single input buffer op-amp solution can't be found in part 2, I will have to test the classical source follower, the common source differential amplifier and/or the bootstrap schematics. Eventually this will come as an additional 5th part.
In 2016 year I started a research for the analog front-end of the voltmeter and now I'm in a process to make the first prototype. In the first posts at this time, I focused on over-voltage protection, dual polarity input handling and the automatic voltage range. I used a simulator/breadboard prototyping and looked for existing schematics in application notes or in the internet. I didn't really thought of the errors caused by the analog front end. So right now I'm going to identify, analyze and test them.
Why do they matter? Well, the measurement process is not only taking the measurement result from the DMM display, but also the calculation of uncertainty based on all data available in the DMM specification and the possible errors due unit under test characteristics.
Most of the errors come from the resistance of the unit under test. Measuring a voltage source with high source resistance (like high value resistor dividers during calibration process) or high value resistance can be challenging for some existing DMM models. For this reason I will limit the maximum error to 10ppm when the source resistance is 1MOhms. This will be my criteria for the input buffer components selection. The limit will be 1ppm for errors that do not correlate with the source resistance.
Just an example on why this matters: even if you want to calibrate the 1V range from 10V voltage standard using the Fluke 752A reference divider with output ratio uncertainty of 0.2ppm, there will be still a significant error from DMM bias current due to the high output resistance of the Fluke 752A. The output resistance is 40KOhm and if you are trying to calibrate the 1V range for a DMM with 10pA leakage current, it will create a parasitic voltage with a value of 0.4uV. And this value is 0.4 ppm regarding to the output which will be added in the final uncertainty.
Firstly, let's try to identify the possible errors which can be found in the analog front end and the requirements that affect the specification. I'm aware for 8 of them so far:
I'm interested only for those errors that affect the input buffer in the front of the ADC. I want to make an error budget which will allow me to select a preferable op-amp.
- Thermal EMF.
- Current leakage.
- Loading error.
- Long term and temperature drift of resistors used in the pre-amplifier.
- DC amplifier's errors due to voltage offset, none-linearity, noise and common mode rejection ratio.
I'm interested only for those errors that affect the input buffer in the front of the ADC. I want to make an error budget which will allow me to select a preferable op-amp.
- Thermal EMF errors which affect low-level dc voltage measurements. They are caused by the connection of dissimilar metals at different temperatures. This can be happen when:
- connections between the unit under test and the DMM PCB are made from different materials. Connections made by copper or silver wires and usage of low thermal EMF binding posts made by tellurium copper are preferable. Wire crimping between the binding posts and the DMM PCB is better than wire soldering.
- electro-mechanical relays are used for high voltage ranges. In this case low EMF relay are preferable.
- Errors caused by leakage currents
When a high resistance circuit is measured, any current leakage will generate a parasitic voltage offset which will cause an error in the measurement process. The formula is V error = I leakage * R source. Origins of the leakage currents can be:
When a high resistance circuit is measured, any current leakage will generate a parasitic voltage offset which will cause an error in the measurement process. The formula is V error = I leakage * R source. Origins of the leakage currents can be:
- input bias current in the input buffer. This can be caused by JFET pair or op-amp, depends on schematics.
- reverse leakage current in over-voltage clamping diodes.
- contaminated PCB. This can be solved with PCB cleaning and active guarding.
- cable leakage or leakage caused by binding posts insulation.
I managed to collect information about the input bias current for several 6.5, 7.5 and 8.5 digits DMM and then made some real measurements with 10MOhs resistor connected to input binding posts. And here are results:
For the real measurements I used a small PCB with soldered 10MOhms resistor. Voltage range was set to 10V or 20V depends on DMM model, High impedance mode, highest possible NPLC value and all DMM were warm-up between 2 and 4 hours before taking the measurements.
I tested 2 HP 34401, 2 Siglent 3065x, 2 Rigol DM3068, 1 Advantest R6581, 1 Keithley 2000 and 2002. Only both Siglent 3065x were out of the spec.
The screenshots for Siglent DMM are taken from two different units. One of them had ~90-100pA leakage and the second one had ~140-150pA leakage.
Limiting the error due leakage currents to less than 10ppm error, when input resistance is 1MOhs, means that my analog front-end must have less than 100pA current leakage. I will reserve 50pA for op-amp bias current, 30pA for clamp diodes and 20pA for the rest of the error origins.
When ultra low-current or ultra-high resistance has to be measured, another type of measuring devices called "Electrometers" are used. They have fA range bias current and can measure giga-ohms resistors. Models from top-brand manufactures are: Keysight B2980A Series and Keithley 6514 / 6517B.
- Loading error
This error can be calculated with the following formula : R source / (R source + R dmm). Most of the bench DMM have at least 10GOhm input resistance, which guarantees less than 1ppm error when unit under test have less than 10KOhms resistance.
This error can be calculated with the following formula : R source / (R source + R dmm). Most of the bench DMM have at least 10GOhm input resistance, which guarantees less than 1ppm error when unit under test have less than 10KOhms resistance.
Note that the common-mode input resistance is equal to the change in input bias current relative to the change in the buffer's input voltage Some of the op-amp manufactures specified the minimum value of this parameter, but not all of them.
For this error I will look for an op-amp which has at least 100GOhms input resistance. This will limit the error in the range of 10ppm if the source resistance is 1MOhms.
For this error I will look for an op-amp which has at least 100GOhms input resistance. This will limit the error in the range of 10ppm if the source resistance is 1MOhms.
- Errors due to resistors used in the pre-amplifier
When the input voltage is significantly less than the native ADC range (10 or 20V), an DC amplifier is used to increase it. Resistors used in the amplifier suffer from temperature and long term drifting. They also can contribute to the error noise budget of the whole system if high values are selected.
- Vos drift due to temperature changes (Vos TC).
- Vos long-term drift. Not all manufactures mention their long term drift of the Vos.
These errors are almost eliminated in the zero drift op-amp, but these classes of op-amp usually suffer from higher current density noise.
I would select maximum 1uV/C for Vos TC if none zero drift op-amp has to be selected.
I would select maximum 1uV/C for Vos TC if none zero drift op-amp has to be selected.
- Common Mode Rejection Ratio (CMRR)
This parameter of the none inverting input buffer specify how well the op-amp will reject the parasitic signals from both the input and the ground. Most of the modern op-amp have CMRR value of at least 120dB which suppresses 1V input parasitic common mode voltage signal to 1uV output error (1ppm). For the 10ppm error, the CMRR has to be at least 100dB.
The formula for the error caused by CMRR is:
V out error = Vcm /(10-CMRR/20).
Note that CMRR is decreasing while increasing the frequency of the input signal. CMRR is increasing proportionally with the op-amp gain.
- Linearity errorThis parameter of the none inverting input buffer specify how well the op-amp will reject the parasitic signals from both the input and the ground. Most of the modern op-amp have CMRR value of at least 120dB which suppresses 1V input parasitic common mode voltage signal to 1uV output error (1ppm). For the 10ppm error, the CMRR has to be at least 100dB.
The formula for the error caused by CMRR is:
V out error = Vcm /(10-CMRR/20).
Note that CMRR is decreasing while increasing the frequency of the input signal. CMRR is increasing proportionally with the op-amp gain.
When an op-amp is used in unity gain mode, the none-linearity error is usually in the ppm and sub-ppm range. The none-linearity error is proportional to the gain and can be of a significant value if gains of 10 and 100 are used for 1V and 0.1V ranges.
More information can be found in the following link.
Noise level determine the maximum resolution of the DMM.
The effective number of digits (ENOD) can be calculated by the following formula for 99.7% probability:
Digits = Log10( Full Scale Voltage Range/ Peak-Peak of the noise)The following noise sources caused by the input op-amp are:
- input voltage noise
- input current noise
- thermal noise of the gain resistors in the DC amplifier
For now I will skip the gain resistor noise and I will focus only on input voltage and current noise when high source resistance exists. The total sum of the RMS noise can be calculated with the root sum squared method:
Noise RMS = SQRT (VnoiseRMS2+(InoiseRMS*Rsrc)2+ Rsrc thermal noise RMS2)
The RMS noise of 1MOhms resistor is 0.41uV for 10Hz frequency bandwidth.
The peak to peak value can be estimated by multiplying by 6.6 the total RMS noise value. This will give us 99.9% confidence level.
If the noise is given only with its spectral density, the RMS value is calculated with multiplication of the spectral density and square root of the desire bandwidth (10Hz). This is valid only when the noise is a flat curve between 0.1 and 10Hz.
For example if the current spectral noise is 100fA/√Hz, the RMS value is 100fa * √ 10 Hz = 316.23 fA RMS. If the source resistance is 1MOhms, the RMS voltage noise will be 0.316 uV or 2.1 uV p2p.
For example if the current spectral noise is 100fA/√Hz, the RMS value is 100fa * √ 10 Hz = 316.23 fA RMS. If the source resistance is 1MOhms, the RMS voltage noise will be 0.316 uV or 2.1 uV p2p.
When the source resistance is relatively low, the dominant will be the input voltage noise. High value of the source resistance multiplied by the input current noise can exceed the input voltage noise.
- 44uV p2p noise for 6 digits ENOD and 22 V range / 44V full scale
- 4.4uV p2p noise for 7 digits ENOD and 22 V range / 44V full scale
- 24uV p2p noise for 6 digits ENOD and 12 V range / 24V full scale
- 2.4uV p2p noise for 7 digits ENOD and 12 V range / 24V full scale
ADI tutorial for op-amp noise can be found the following link.
An excellent explanation video in 4 parts about op-amp noise can be watched here.
I was able to find only two low level noise voltmeters, called also nano voltmeters: HP 34420 and Keithley 2182A . They both are 7.5 digits. For 1MOhs source resistance HP 34420 is specified to 90nV RMS noise and for Keithley 2182A the noise is 350 nV RMS.
In the next post I'm going to select one from several op-amps depending on error budget and I'm going to perform some tests to check if real parameters are better than the datasheet.
Here is the summary of my error budget for the input op-amp excluding the noise limitations, mention above:
Update : a friend of mine send me a article from EDN : Design femtoampere circuits with low leakage. I think it is worth to add a link here: part 1, part 2 and part 3.
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